AM79C972BVCW datasheet(82/130 Pages) AMD

82 / 130 page

Am79C972

n BCR37

PCI DATA Register Zero (DATA0)

Alias Register

n BCR38

PCI DATA Register One (DATA1)

Alias Register

n BCR39

PCI DATA Register Two (DATA2)

Alias Register

n BCR40

PCI

DATA

Three

(DATA3) Alias Register

n BCR41

PCI DATA Register Four (DATA4)

Alias Register

n BCR42

PCI DATA Register Five (DATA5)

Alias Register

n BCR43

PCI DATA Register Six (DATA6)

Alias Register

n BCR44

PCI

DATA

Seven

(DATA7) Alias Register

n BCR45

OnNow

Pattern

Matching

n BCR46

OnNow

Pattern

Matching

n BCR47

OnNow

Pattern

Matching

n CSR116

OnNow Miscellaneous

If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)

are cleared to 0, then the EEPROM read has experi-

enced a failure and the contents of the EEPROM pro-

grammable BCR register will be set to default

H_RESET values. The content of the Address PROM

locations, however, will not be cleared.

Accesses to the Address PROM I/O locations do not di-

rectly access the Address EEPROM itself. Instead,

these accesses are routed to a set of shadow registers

on board the Am79C972 controller that are loaded with

a copy of the EEPROM contents during the automatic

read operation that immediately follows the H_RESET

operation.

EEPROM MAP

The automatic EEPROM read operation will access 34

words (i.e., 68 bytes) of the EEPROM. The format of

the EEPROM contents is shown in Table 10 (next

page), beginning with the byte that resides at the low-

est EEPROM address.

Note: The first bit out of any word location in the EE-

PROM is treated as the MSB of the register being pro-

grammed. For example, the first bit out of EEPROM

word location 09h will be written into BCR4, bit 15; the

second bit out of EEPROM word location 09h will be

written into BCR4, bit 14, etc.

There are two checksum locations within the EE-

PROM. The first checksum will be used by AMD driver

software to verify that the ISO 8802-3 (IEEE/ANSI

802.3) station address has not been corrupted. The

value of bytes 0Ch and 0Dh should match the sum of

bytes 00h through 0Bh and 0Eh and 0Fh. The second

checksum location (byte 43h) is not a checksum total,

but is, instead, a checksum adjustment. The value of

this byte should be such that the total checksum for the

entire 68 bytes of EEPROM data equals the value FFh.

The checksum adjust byte is needed by the Am79C972

controller in order to verify that the EEPROM content

has not been corrupted.

LED Support

The Am79C972 controller can support up to four LEDs.

LED outputs LED0, LED1, and LED2 allow for direct

connection of an LED and its supporting pullup device.

In applications that want to use the pin to drive an LED

and also have an EEPROM, it might be necessary to

buffer the LED3 circuit from the EEPROM connection.

When an LED circuit is directly connected to the

EEDO/LED3/SRD pin, then it is not possible for most

EEPROM devices to sink enough IOL to maintain a valid

low level on the EEDO input to the Am79C972 control-

ler. Use of buffering can be avoided if a low power LED

is used.

Each LED can be programmed through a BCR register

to indicate one or more of the following network status

or activities: Collision Status, Full-Duplex Link Status,

Half-Duplex Link Status, Receive Match, Receive Sta-

tus, Magic Packet, Disable Transceiver, and Transmit

Status.

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