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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM79C972BVCW 데이터시트(PDF) 120 Page - Advanced Micro Devices |
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AM79C972BVCW 데이터시트(HTML) 120 Page - Advanced Micro Devices |
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120 / 130 page  120 Am79C972 write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR12: Physical Address Register 0 Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PADR[15:0] Physical Address Register, PADR[15:0]. The contents of this register are loaded from EE- PROM after H_RESET or by an EEPROM read command (PRGAD, BCR19, bit 14). If the EEPROM is not present, the con- tents of this register are unde- fined. This register can also be loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR13: Physical Address Register 1 Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PADR[31:16]Physical Address Register, PADR[31:16]. The contents of this register are loaded from EE- PROM after H_RESET or by an EEPROM read command (PRGAD, BCR19, bit 14). If the EEPROM is not present, the con- tents of this register are unde- fined. This register can also be loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR14: Physical Address Register 2 Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PADR[47:32]Physical Address Register, PADR[47:32].The contents of this register are loaded from EE- PROM after H_RESET or by an EEPROM read command (PRGAD, BCR19, bit 14). If the EEPROM is not present, the con- tents of this register are unde- fined. This register can also be loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR15: Mode This register’s fields are loaded during the Am79C972 controller initialization routine with the corresponding Initialization Block values, or when a direct register write has been performed on this register. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15 PROM Promiscuous Mode. When PROM = 1, all incoming receive frames are accepted. |
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