AM79C976 datasheet(211/309 Pages) AMD

211 / 309 page

8/01/00

Am79C976

211

P R E L I M INARY

Table 90 indicates the possible

combinations of EEDET and the

existence of an EEPROM and the

resulting operations that are pos-

sible on the EEPROM interface.

Table 90. EEDET Setting

12-5

RES

Reserved locations. Written as

zeros; read as undefined.

EEN

EEPROM Port Enable. When this

bit is set to a 1, it causes the val-

ues of ECS, ESK, and EDI to be

driven onto the EECS, EESK,

and EEDI pins, respectively. If

EEN = 0 and no EEPROM read

function is currently active, then

EECS will be driven LOW. When

EEN = 0 and no EEPROM read

function is currently active, EESK

and EEDI pins will be driven by

the LED registers BCR5 and

BCR4, respectively. See Table

91.

Read/Write accessible. EEN is

set to 0 by H_RESET and is unaf-

fected by S_RESET or STOP.

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RES

Reserved location. Written as

zero and read as undefined.

ECS

EEPROM Chip Select. This bit is

used to control the value of the

EECS pin of the interface when

the EEN bit is set to 1 and the

PREAD bit is set to 0. If EEN = 1

and PREAD = 0 and ECS is set

to a 1, then the EECS pin will be

forced to a HIGH level at the ris-

ing edge of the next clock follow-

ing bit programming.

If EEN = 1 and PREAD = 0 and

ECS is set to a 0, then the EECS

pin will be forced to a LOW level

at the rising edge of the next

clock following bit programming.

ECS has no effect on the output

value of the EECS pin unless the

PREAD bit is set to 0 and the

EEN bit is set to 1.

Read/Write accessible. ECS is

set to 0 by H_RESET and is not

affected by S_RESET or STOP.

EEDET Value

(BCR19[13])

EEPROM

Connected?

Result if PREAD is Set to 1

Result of Automatic EEPROM Read

Operation Following H_RESET

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

failure will result; PVALID is reset to 0.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

Yes

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

operation will pass; PVALID is set to 1.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

failure will result; PVALID is reset to 0.

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

failure will result; PVALID is reset to 0.

Yes

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

operation will pass; PVALID is set to 1.

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

operation will pass; PVALID is set to 1.

Table 91. Interface Pin Assignment

567 Pin

*PREAD or Auto

Read in Progress

EEN

EECS

EESK

EEDI

Low

Tri-State

High

Active

High

From ECS

Bit of BCR19

From ESK Bit of

BCR19

From EEDI Bit of

BCR19

High

LED1

LED0

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