AM79C976 datasheet(38/309 Pages) AMD

38 / 309 page

Am79C976

8/01/00

P R E L I M INARY

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The Am79C976 controller does not support burst ac-

cess to the configuration space, the first 32 bytes of its

I/O or memory space, or to the Expansion Bus. The

host indicates a burst transaction by keeping FRAME

asserted during the data phase. When the Am79C976

controller sees FRAME and IRDY asserted in the clock

cycle before it wants to assert TRDY, it also asserts

STOP at the same time. The transfer of the first data

phase is still successful, since IRDY and TRDY are

both asserted. See Figure 66.

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If the host is not yet ready when the Am79C976 control-

ler asserts TRDY, the device will wait for the host to as-

sert IRDY. When the host asserts IRDY and FRAME is

still asserted, the Am79C976 controller will finish the

first data phase by deasserting TRDY one clock later.

At the same time, it will assert STOP to signal a discon-

nect to the host. STOP will stay asserted until the host

removes FRAME. See Figure 77.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

CMD

PAR

DATA

ADDR

22929B7

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

PAR

DATA

1st DATA

22929B8

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