AM79C976 datasheet(185/309 Pages) AMD

185 / 309 page

8/01/00

Am79C976

185

P R E L I M INARY

or a direct register write has been

performed on this register.

Read/Write

accessible.

These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

&653K\VLFDO$GGUHVV 5HJLVWHU

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PADR[31:16]Physical

Address

PADR[31:16]. The contents of

this register are loaded from EE-

PROM after H_RESET or by an

EEPROM

read

command

(PREAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write

accessible.

These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

&653K\VLFDO$GGUHVV 5HJLVWHU

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PADR[47:32]Physical

Address

PADR[47:32].The

contents

this register are loaded from

EEPROM after H_RESET or by

EEPROM

read

command

(PREAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write

accessible.

These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

&650RGH

This register’s fields are loaded during the Am79C976

controller initialization routine with the corresponding

Initialization Block values, or when a direct register write

has been performed on this register.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

PROM

Promiscuous

Mode.

When

PROM = 1, all incoming receive

frames are accepted.

Read/Write accessible.

DRCVBC

Disable

Receive

Broadcast.

When

set,

disables

the

Am79C976 controller from re-

ceiving

broadcast

messages.

Used for protocols that do not

support broadcast addressing,

except as a function of multicast.

DRCVBC is cleared by activation

H_RESET

S_RESET

(broadcast messages will be re-

ceived) and is unaffected by

STOP.

Read/Write accessible.

DRCVPA

Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the Am79C976 controller

will be disabled. Frames ad-

dressed to the node’s individual

physical address will not be rec-

ognized.

Read/Write accessible.

12-9

RES

Reserved locations. Written as

zeros and read as undefined.

8-7

PORTSEL[1:0]Obsolete function. Writing has

no effect. Read as undefined.

INTL

Obsolete function. Writing has no

effect. Read as undefined.

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