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STM32F107RC 데이터시트(PDF) 97 Page - STMicroelectronics |
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STM32F107RC 데이터시트(HTML) 97 Page - STMicroelectronics |
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97 / 103 page ![]() STM32F105xx, STM32F107xx Application block diagrams Doc ID 15274 Rev 6 97/104 Table 64 give the IDD run mode values that correspond to the conditions specified in Table 63. Table 63. PLL configurations Application Crystal value in MHz (XT1) PREDIV2 PLL2MUL PLLSRC PREDIV1 PLLMUL USB prescaler (PLLVCO output) PLL3MUL I2Sn clock input MCO (main clock output) Ethernet only 25 /5 PLL2ON x8 PLL2 /5 PLLON x9 NA PLL3ON x10 NA XT1 (MII) PLL3 (RMII) Ethernet + OTG 25 /5 PLL2ON x8 PLL2 /5 PLLON x9 /3 PLL3ON x10 NA XT1 (MII) PLL3 (RMII) Ethernet + OTG + basic audio 25 /5 PLL2ON x8 PLL2 /5 PLLON x9 /3 PLL3ON x10 PLL XT1 (MII) PLL3 (RMII) Ethernet + OTG + Audio class I2S(1) 14.7456 /4 PLL2ON x12 PLL2 /4 PLLON x6.5 /3 PLL3ON x20 PLL3 VCO Out NA ETH PHY must use its own crystal OTG only 8 NA PLL2OFF XT1 /1 PLLON x9 /3 PLL3OFF NA NA OTG + basic audio 8 NA PLL2OFF XT1 /1 PLLON x9 /3 PLL3OFF PLL NA OTG + Audio class I2S(1) 14.7456 /4 PLL2ON x12 PLL2 /4 PLLON x6.5 /3 PLL3ON x20 PLL3 VCO Out NA Audio class I2S only(1) 14.7456 /4 PLL2ON x12 PLL2 /4 PLLON x6.5 NA PLL3ON x20 PLL3 VCO out NA 1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz. |
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