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IO96PDB2V1 데이터시트(PDF) 38 Page - Microsemi Corporation

부품명 IO96PDB2V1
상세설명  ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology
PDF  242 Pages
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제조업체  MICROSEMI [Microsemi Corporation]
홈페이지  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

IO96PDB2V1 데이터시트(HTML) 38 Page - Microsemi Corporation

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ProASIC3L DC and Switching Characteristics
2-22
Revision 13
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Pro I/O Banks
I/O Standard
Drive
Strength
(mA)
Equiv.
Software
Default
Drive
Strength
Option1
Slew
Rate
VIL
VIH
VOL
VOH
IOL3 IOH3
Min.
V
Max.
V
Min.
V
Max.2
V
Max.
V
Min.
VmA mA
3.3 V LVTTL /
3.3 V
LVCMOS
12 mA
12 mA High –0.3
0.8
2
3.6
0.4
2.4
12
12
3.3 V
LVCMOS
Wide Range4
100 µA
12 mA High –0.3
0.8
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V
LVCMOS
12 mA
12 mA High –0.3
0.7
1.7
2.7
0.7
1.7
12
12
1.8 V
LVCMOS
12 mA
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI
1.9
0.45
VCCI – 0.45 12
12
1.5 V
LVCMOS
12 mA
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12
12
1.2 V
LVCMOS
2 mA
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2
2
1.2 V
LVCMOS
Wide Range5
100 µA
2 mA
High –0.3 0.3 * VCCI
0.7 * VCCI 1.575
0.1
VCCI – 0.1 0.1 0.1
3.3 V PCI
Per PCI Specification
3.3 V PCI-X
Per PCI-X Specification
3.3 V GTL
20 mA6
20 mA6 High –0.3 VREF – 0.05 VREF + 0.05
3.6
0.4
–
20
20
2.5 V GTL
20 mA6
20 mA6 High –0.3 VREF – 0.05 VREF + 0.05
2.7
0.4
–
20
20
3.3 V GTL+
35 mA
35 mA High –0.3 VREF – 0.1
VREF + 0.1
3.6
0.6
–
35
35
2.5 V GTL+
33 mA
33 mA High –0.3 VREF – 0.1
VREF + 0.1
2.7
0.6
–
33
33
HSTL (I)
8 mA
8 mA
High –0.3 VREF – 0.1
VREF + 0.1 1.575
0.4
VCCI – 0.4
8
8
HSTL (II)
15 mA6
15 mA6 High –0.3 VREF – 0.1
VREF + 0.1 1.575
0.4
VCCI – 0.4
15
15
SSTL2 (I)
15 mA
15 mA High –0.3 VREF – 0.1
VREF + 0.1
2.7
0.54
VCCI – 0.62 15
15
SSTL2 (II)
18 mA
18 mA High –0.3 VREF – 0.1
VREF + 0.1
2.7
0.35
VCCI – 0.43 18
18
SSTL3 (I)
14 mA
14 mA High –0.3 VREF – 0.1
VREF + 0.1
3.6
0.7
VCCI – 1.1 14
14
SSTL3 (II)
21 mA
21 mA High –0.3 VREF – 0.1
VREF + 0.1
3.6
0.5
VCCI – 0.9 21
21
Notes:
1. Please note that 1.2V LVCMOS and 3.3V LVCMOS wide range is applicable to 100uA drive strength only. The
configuration will NOT operate at the equivalent software.
2. Maximum VIH is 3.6 V for all I/O standards with hot-insertion is enabled.
3. Currents are measured at 85°C junction temperature.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
6. Output drive strength is below JEDEC specification.
7. Output slew rate can be extracted using the IBIS models.



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