IO96PDB2V1 datasheet(169/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

3-3

When Flash*Freeze mode is used, the FF pin must not be left floating, to avoid accidentally entering

Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.

The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in

which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin

should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,

simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be

considered.

Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both

Flash*Freeze mode and normal operation mode. No user intervention is required.

Table 3-1 shows the Flash*Freeze pin location on the available packages ProASIC3L devices. The

Flash*Freeze pin location is independent of device (except for the PQ208 package), allowing migration to

larger or smaller devices while maintaining the same pin location on the board. Refer to the

"Flash*Freeze Technology and Low Power Modes" chapter of the ProASIC3L FPGA Fabric User’s Guide

for more information on I/O states during Flash*Freeze mode.

Table 3-1 • Flash*Freeze Pin Location

ProASIC3L Package

Flash*Freeze Pin

VQ100

FG144

FG256

FG324

FG484

FG896

AH4

PQ208

PQ208-A3P250

PQ208-A3P600L

PQ208-A3P1000L

PQ208-A3P3000L

IO96PDB2V1 데이터시트(PDF) 169 Page - Microsemi Corporation