V6212615-01XE-R datasheet(22/92 Pages) TI

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TX_CLK

TX_EN

TXD

PMD output pair

(J/K)

T2.6.1

IDLE

DATA

RX_CLK

RXD[3:0]

RX_DV

RX_ER

Valid data

T2.5.2

T2.5.1

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

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3.5.5

100 Mb/s MII Receive Timing

Figure 3-6. 100 Mb/s MII Receive Timing

xxx

PARAMETER

DESCRIPTION

NOTES

MIN

TYP

MAX

UNIT

T2.5.1

RX_CLK High/Low Time

100 Mb/s Normal mode

T2.5.2

RX_CLK to RXD[3:0], RX_DV,

100 Mb/s Normal mode

RX_ER Delay

3.5.6

100BASE-TX Transmit Packet Latency Timing

Figure 3-7. 100BASE-TX Transmit Packet Latency Timing

xxx

PARAMETER

DESCRIPTION

NOTES(1)

MIN

TYP

MAX

UNIT

T2.6.1

TX_CLK to PMD Output Pair

100 Mb/s Normal mode

bits

Latency

(1)

For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of

TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

ELECTRICAL SPECIFICATIONS

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