CS4218 datasheet(16/44 Pages) CIRRUS

16 / 44 page

SCLK must be generated externally. When the

codec is the serial port master, the serial port sig-

nal transitions are controlled with respect to the

internal analog sampling clock to minimize the

amount of digital noise coupled into the analog

section. Since SSYNC and SCLK are externally

derived when the codec slaves to the serial port,

optimum noise management cannot be obtained;

therefore, master modes should be used when-

ever possible. Multiplier sub-modes are identical

to the SM3 modes except the master clock,

CLKIN, is internally multiplied by 16. A

0.47

µF capacitor must be tied to the FILT pin

when using the Multiplier sub-modes.

Master Clock Frequency

In SM3-M and SM3-S sub-modes, the master

clock, CLKIN, must be 256

× Fsmax. For exam-

ple, given a 48 kHz maximum sample frequency,

th e

maste r

clo ck

fr eq ue nc y

mu st

12.288 MHz. In SM3-MM and SM3-MS sub-

mo de s, CLKIN mu st be 16xFsmax.

Fo r

example, given a 48 kHz maximum sample fre-

quency, the master clock frequency must be

768 kHz. SCLK and SSYNC must be synchro-

nous to the master clock.

Sub-frame

Word B

Word A

DAC - Left Word

00 0 0

DAC - Right Word

Sub-frame

Figure 11. Serial Data Input Format - SM3, SM5.

Sub-frame

Word B

Word A

ADC - Left Word

ADC - Right Word

0 0 010 00 0

000 0

00 00

Sub-frame

Figure 12. Serial Data Output Format - SM3, SM5.

CS4218

DS135F1

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