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CS5180 데이터시트(PDF) 14 Page - Cirrus Logic |
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CS5180 데이터시트(HTML) 14 Page - Cirrus Logic |
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14 / 28 page ![]() CS5180 14 supply pins should be bypassed to the nearest ground pin on the chip. The bypass capacitors should be located as close to the chip as possible. If the chip is surface mounted the bypass capacitors should be on the same side of the circuit card as the chip. The CS5180 is a high speed component that re- quires adherence to standard high-frequency print- ed circuit board layout techniques to maintain optimum performance. These include the use of ground and power planes, using low noise power supplies in conjunction with proper supply decou- pling, minimizing circuit trace lengths, and physi- cal separation of digital and analog components and circuit traces. It is preferred that any clock oscillator circuitry be located on a ground plane separate from the digital plane in order to ensure that digital noise does not induce clock jitter. For additional insight, see the CDB5180 evaluation board for more details. Also refer to Application Note AN18 about layout and design rules for data converters. AGND1 +5 V + + + ~ 3.8 V Fully Differential CMV = 2.375 V pp +5 V or +3.0 V VA1+ VA2+ AGND2 AGND3 VREFOUT VREFIN VREF- VREF+ VREFCAP AIN+ AIN- DGND1 VD1+ VD2+ DGND2 PWDN MODE RESET SYNC MFLAG MCLK MCLK FSO SCLK SDO SCLK SDO Control Logic Clock Source Data Interface CS5180 1 28 8 7 18 4 5 3 2 6 26 27 22 21 12 11 25 24 23 10 9 20 19 17 14 13 16 15 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 10 µF 10 µF 1µF 2200 pF 2200 pF 20 Ω 20 Ω The 3.8 Vpp fully differential input span is set by the converter’s internal voltage reference at 2.375 V. An input span of 4.0 Vpp fully differential would result if an external voltage reference of 2.5 V is used. † Miniature surface mount 25.6 MHz clock oscillators may be ordered from the CTS Reeves Company. For 4.5 V to 5.5 Volt Operation, order P/N 974-7725-0000A For 3.0 to 3.6 Volt Operation, order P/N 974-7727-0000A Figure 11. CS5180 System Connection Diagram † |
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