Instructions

M24C01/02-W M24C01/02-R M24C02-F

16/34

DocID024020 Rev 2

5.1.3

Minimizing Write delays by polling on ACK

parameters

, but the typical time is shorter. To make use of this, a polling sequence can be

used by the bus master.

The sequence, as shown in Figure 7, is:

•

Initial condition: a Write cycle is in progress.

•

Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

•

Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal Write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 7. Write cycle polling flowchart using ACK

Write cycle

in progress

AI01847d

AI01847e

Next

Operation is

addressingthe

memory

Start condition

Device select

with RW = 0

ACK

returned

YES

NO

YES

NO

ReStart

Stop

Data for the

Write cperation

Device select

with RW = 1

Send Address

and Receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YES

NO

StartCondition

Continue the

Write operation

Continue the

Random Read operation