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M24C08 데이터시트(PDF) 25 Page - STMicroelectronics

부품명 M24C08
상세설명  1-Kbit and 2-Kbit serial IC bus EEPROMs
PDF  34 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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M24C08 데이터시트(HTML) 25 Page - STMicroelectronics

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M24C01/02-W M24C01/02-R M24C02-F
DC and AC parameters
33
Table 16. 400 kHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
-
400
kHz
tCHCL
tHIGH
Clock pulse width high
600
-
ns
tCLCH
tLOW
Clock pulse width low
1300
-
ns
tQL1QL2(1)
1. Characterized only, not tested in production.
tF
SDA (out) fall time
20(2)
2. With CL = 10 pF.
300
ns
tXH1XH2
tR
Input signal rise time
(3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
(3)
ns
tXL1XL2
tF
Input signal fall time
(3)
(3)
ns
tDXCX
tSU:DAT Data in set up time
100
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
tCLQX(4)
4. The min value for tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the
undefined region of the falling edge SCL.
tDH
Data out hold time
100
-
ns
tCLQV(5)
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 10.
tAA
Clock low to next data valid (access time)
-
900
ns
tCHDL
tSU:STA Start condition setup time
600
-
ns
tDLCL
tHD:STA Start condition hold time
600
-
ns
tCHDH
tSU:STO Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tW
tWR
Write time
-
5
ms
tNS(1)
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
100
ns



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