IO13RSB0 datasheet(35/210 Pages) MICROSEMI

35 / 210 page

ProASIC3 Flash Family FPGAs

Re vi s i on 15

2 - 30

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-34 • I/O Short Currents IOSH/IOSL

Applicable to Standard I/O Banks

Drive Strength

IOSL (mA)1

IOSH (mA)1

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

3.3 V LVCMOS Wide Range2

100 µA

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

2.5 V LVCMOS

2 mA

4 mA

6 mA

8 mA

1.8 V LVCMOS

2 mA

4 mA

1.5 V LVCMOS

2 mA

Notes:

1. TJ = 100°C

2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected

for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as

specified in the JESD-8B specification.

Table 2-35 • Duration of Short Circuit Event Before Failure

Temperature

Time before Failure

–40°C

> 20 years

0°C

> 20 years

25°C

> 20 years

70°C

5 years

85°C

2 years

100°C

0.5 years

Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.)

Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS

No requirement

10 ns *

20 years (110°C)

LVDS/B-LVDS/

M-LVDS/LVPECL

No requirement

10 ns *

10 years (100°C)

Note:

*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum

value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.

Microsemi recommends signal integrity evaluation/characterization of the system to ensure that

there is no excessive noise coupling into input signals.

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