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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IO13RSB0 데이터시트(PDF) 111 Page - Microsemi Corporation |
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IO13RSB0 데이터시트(HTML) 111 Page - Microsemi Corporation |
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111 / 210 page  ProASIC3 Flash Family FPGAs Re vi s i on 15 2 - 106 Embedded FlashROM Characteristics Timing Characteristics tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on DO (pass-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency 310 272 231 MHz Figure 2-43 • Timing Diagram Table 2-123 • A3P250 FIFO 4k×1 (continued) Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units A0 A1 tSU tHOLD tSU tHOLD tSU tHOLD tCKQ2 tCKQ2 tCKQ2 CLK Address Data D0 D0 D1 Table 2-124 • Embedded FlashROM Access Time Parameter Description –2 –1 Std. Units tSU Address Setup Time 0.53 0.61 0.71 ns tHOLD Address Hold Time 0.00 0.00 0.00 ns tCK2Q Clock to Out 21.42 24.40 28.68 ns FMAX Maximum Clock Frequency 15 15 15 MHz |
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