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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IO13PDB0V0 데이터시트(PDF) 87 Page - Microsemi Corporation |
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IO13PDB0V0 데이터시트(HTML) 87 Page - Microsemi Corporation |
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87 / 197 page  SmartFusion Customizable System-on-Chip (cSoC) Re vi s i on 12 2 - 75 Timing Characteristics Embedded Nonvolatile Memory Block (eNVM) Electrical Characteristics Table 2-90 describes the eNVM maximum performance. Table 2-89 • FIFO Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V Parameter Description –1 Std. Units tENS REN, WEN Setup Time 1.40 1.68 ns tENH REN, WEN Hold Time 0.02 0.02 ns tBKS BLK Setup Time 0.19 0.19 ns tBKH BLK Hold Time 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.19 0.22 ns tDH Input Data (WD) Hold Time 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.39 2.87 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.91 1.09 ns tRCKEF RCLK High to Empty Flag Valid 1.74 2.09 ns tWCKFF WCLK High to Full Flag Valid 1.66 1.99 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.29 7.54 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.72 2.06 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.22 7.47 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.94 1.12 ns RESET Low to Data Out Low on RD (pipelined) 0.94 1.12 ns tREMRSTB RESET Removal 0.29 0.35 ns tRECRSTB RESET Recovery 1.52 1.83 ns tMPWRSTB RESET Minimum Pulse Width 0.22 0.22 ns tCYC Clock Cycle Time 3.28 3.28 ns FMAX Maximum Frequency for FIFO 305 305 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values. Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC = 1.425 V Parameter Description A2F060 A2F200 A2F500 Units –1 Std. –1 Std. –1 Std. tFMAXCLKeNVM Maximum frequency for clock for the control logic – 5 cycles (5:1:1:1*) 80 80 80 80 50 50 MHz tFMAXCLKeNVM Maximum frequency for clock for the control logic – 6 cycles (6:1:1:1*) 100 80 100 80 100 80 MHz Note: *6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles for the first access and 1 each for the next three accesses. |
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