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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AS3911B 데이터시트(PDF) 45 Page - ams AG |
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AS3911B 데이터시트(HTML) 45 Page - ams AG |
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45 / 155 page  ams Datasheet: 2014-Jun-12 [v1-08] AS3911B – 45 Appl icatio n I n f o rm a t i o n SPI Timing Figure 31: SPI Timing Figure 32: SPI General Timing Symbol Parameter Min Typ Max Unit Notes General Timing (VDD = VDD_IO = VDD_D = 3.3 V, Temperature 25°C) TSCLK SCLK period 100 ns TSCLK=TSCLKL+TSCLKH, use of shorter SCLK period may lead to incorrect operation of FIFO TSCLKL SCLK low 40 *1 ns TSCLKH SCLK high 40 ns TSSH SPI reset (/SS high) 100 ns TNCSL /SS falling to SCLK rising 25 ns First SCLK pulse TNCSH SCLK falling to /SS rising 25 (tbd) ns Last SCLK pulse TDIS Data in setup time 10 ns TDIH Data in hold time 10 ns Read Timing (VDD = VDD_IO = VDD_D = 3.3 V, Temperature 25°C, CLOAD ≤50 pF) TDOD Data out delay 20 ns TDOHZ Data out to high impedance delay 20 ns ... ... ... DATAI DATAI DATAI ... tSCLKH tNCSL tSCLKL tDIS tDIH tNCSH /SS MOSI MISO SCLK |
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