WM8960 datasheet(66/92 Pages) WOLFSON

66 / 92 page

WM8960

Production Data

PD, August 2013, Rev 4.2

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8960, the master clock may be

stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the

DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In

Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.

However, since setting DIGENB has no effect on the power consumption of other system components

external to the WM8960, it is preferable to disable the master clock at its source wherever possible.

MCLK should not be stopped while the class D outputs are enabled, as this would prevent the

outputs from functioning.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Additional Control

(1)

DIGENB

Master clock disable

0 = Master clock enabled

1 = Master clock disabled

Table 48 Enabling the Master Clock

NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set

to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may

prevent DACs and ADCs from re-starting correctly.

SAVING POWER AT HIGHER SUPPLY VOLTAGE

The AVDD supply of the WM8960 can operate beteen 2.7V and 3.6V. By default, all analogue

circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply

voltages down to 2.7V. At lower voltages, performance can be improved by increasing the bias

current by setting VSEL[1:0] = 01. If low power operation is preferred the bias current can be left at

the default setting. This is controlled as shown below.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R23 (17h)

Additional

Control (1)

7:6

VSEL

[1:0]

Analogue Bias Optimisation

00 = Reserved

01 = Increased bias current optimized for

AVDD=2.7V

1X = Lowest bias current, optimized for

AVDD=3.3V

Table 49 Bias Optimisation

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