GMS30004 datasheet(21/158 Pages) HYNIX

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2 - 2

ROM Address Register

The following registers are used to address the ROM.

• Page address register (PA) :

Holds ROM`s page number (0~Fh) to be addressed.

• Page buffer register (PB) :

Value of PB is loaded by an LPBI command when newly addressing a page.

Then it is shifted into the PA when rightly executing a branch instruction (BR)

and a subroutine call (CAL).

• Program counter (PC) :

Available for addressing word on each page.

• Stack register (SR) :

Stores returned-word address in the subroutine call mode.

(1) Page address register and page buffer register :

Address one of pages #0 to #15 in the ROM by the 4-bit binary counter.

Unlike the program counter, the page address register is usually unchanged

so that the program will repeat on the same page unless a page changing

command is issued. To change the page address, take two steps such as

(1) writing in the page buffer what page to jump to (execution of LPBI) and

(2) execution of BR or CAL, because and instruction code is of eight bits so

that page and word cannot be specified at the same time.

In case a return instruction (RTN) is executed within the subroutine that has

been called in the other page, the page address will be changed at the same

time.

(2) Program counter :

This 6-bit binary counter increments for each fetch to address a word in the

currently addressed page having an instruction to be next executed.

For easier programming, at turning on the power, the program counter is

reset to the zero location. The PA is also set to

Ì0Ì. Then the program

counter specifies the next ROM address in random sequence.

When BR, CAL or RTN instructions are decoded, the switches on each step

are turned off not to update the address. Then, for BR or CAL, address data

are taken in from the instruction operands (a

0 to a5), or for RTN, and

address is fetched from stack register No. 1.

(3) Stack register :

This stack register provides two stages each for the program counter (6 bits)

and the page address register (4bits) so that subroutine nesting can be

mode on two levels.

Chapter 2. Architecture

GMS30004 데이터시트(PDF) 21 Page - Hynix Semiconductor