HM17CM256 datasheet(29/111 Pages) HYNIX

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HM17CM256

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display data structure and gradation control

For the purpose of gradation control, information per pixel requires multiple bits.

This IC has 3 bit

or 2 bit data per output to achieve the gradation display.

This IC is connected to an STN color LCD panel by three segment port units and one pixel consists

of three outputs of segment driver, and so 256 color ( 3 bits x 3 bits x 2 bits ) display on 128 x 82

pixels is realized.

Since one pixel data can be processed by one time access to memory, the data can be rewritten

fast and naturally.

The weight of each data bit is dependent on the status of SWAP register bit and REF register

when data is written to the display RAM.

•

ACCESS when (REF, SWAP)=(0, 0) or (1, 1)

notice) internal access X address :nH~7FH (access when REF=”0”)

:7FH~nH (access when REF=”1”)

•

ACCESS when (REF, SWAP)=(0, 1) or (1, 0)

notice) internal access X address :nH~7FH (access when REF=”0”)

:7FH~nH (access when REF=”1”)

SEGAi

SEGBi

Palette Bj

Palette Aj

SEGCi

Palette Cj

MSB

LSB

MSB

LSB

MSB

GLSB circuit

Gradation palette

i=0~127

j=0~7

CPU access data

X address :nH

Gradation

control circuit.

Display RAM data

SEGAi

SEGBi

SEGCi

Palette Aj

Palette Bj

Palette Cj

MSB

LSB MSB

Gradation palette

i=0~127

j=0~7

CPU access data

X address :nH

Gradation

control circuit

Display RAM data

GLSB circuit

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