| 전자부품 데이터시트 검색엔진 |
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HM17CM256 데이터시트(PDF) 30 Page - Hynix Semiconductor |
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HM17CM256 데이터시트(HTML) 30 Page - Hynix Semiconductor |
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30 / 111 page ![]() HM17CM256 - 30 - When display RAM is accessed by 16 bit data width, the weight of each data bit is dependent on the status of SWAP register and REF register, the same method as 8 bit access • ACCESS when (REF, SWAP)=(0, 0) or (1, 1) notice) internal access X address :nH~3FH (access when REF=”0”) :3FH~nH (access when REF=”1”) • ACCESS when (REF, SWAP)=(0, 1) or (1, 0) notice) internal access X address :nH~3FH (access when REF=”0”) :3FH~nH (access when REF=”1”) MSB LSB MSB LSB MSB GLSB circuit CPU access data X address :nH 1 LSB MSB LSB MSB MSB 1 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SEGAi SEGBi 0 Palette Aj SEGCi Palette Cj Gradation palette i=0~126 j=0~7 Gradation control ciruit Display RAM data 0 0 0 0 1 1 1 1 0 0 SEGBi+1 Palette Bj Palette Cj Palette Bj Palette Aj SEGAi+1 SEGCi+1 1 1 0 0 SEGAi SEGBi 1 Palette Aj SEGCi Palette Cj MSB LSB MSB LSB MSB GLSB circuit Gradation palette i=0~126 j=0~7 CPU access data X address :nH Graydation control ciruit Display RAM data 1 0 0 1 1 1 0 0 1 1 0 LSB MSB LSB MSB MSB SEGBi+1 Palette Bj Palette Cj Palette Bj Palette Aj SEGAi+1 SEGCi+1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 |
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