| 전자부품 데이터시트 검색엔진 |
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28F004SC 데이터시트(PDF) 22 Page - Intel Corporation |
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28F004SC 데이터시트(HTML) 22 Page - Intel Corporation |
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22 / 42 page ![]() BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E 22 PRELIMINARY SR.7 = 0 1 Start Write 20H, Block Address Write D0H, Block Address Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE 1 0 Read Status Register Data (See Above) 1 0 Read Status Register Suspend Block Erase Suspend Block Erase Loop Yes No 1 0 Command Sequence Error SR.3 = SR.5 = SR.4,5 = Block Erase Error Bus Operation Command Comments Standby Check SR.4,5 Both 1 = Command Sequence Error Standby SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Check SR.5 1 = Block Erase Error Standby Bus Operation Command Comments Write Write Erase Setup Read Data = 20H Addr = Within Block to Be Erased Check SR.7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent block erasures. Full status check can be done after each block erase, or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode. Status Register Data Standby Erase Confirm Data = D0H Addr = Within Block to Be Erased Block Erase Successful Standby Check SR.1 1 = Device Protect Detect RP# = V , Block Lock-Bit Is Set Only required for systems implementing lock-bit configuration 0 1 Device Protect Error SR.1 = Check SR.3 1 = V Error Detect PP IH V Range Error PP Figure 7. Automated Block Erase Flowchart |
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