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28F020 데이터시트(PDF) 14 Page - Intel Corporation |
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28F020 데이터시트(HTML) 14 Page - Intel Corporation |
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14 / 38 page ![]() 28F020 E 14 Start Programming (4) Apply V PPH (1) PLSCNT = 0 Write Set-Up Program Cmd Write Program Verify Cmd Read Data from Device Write Read Cmd Verify Data Inc PLSCNT =25? Last Address? Programming Completed Program Error Write Program Cmd (A/D) Time Out 10 µs Apply V PPL (1) Apply V PPL (1) Time Out 6 µs Increment Address N Bus Operation Command Comments Initialize Pulse-Count Write Set-Up Program Data = 40H Write Program Valid Address/Data Standby Duration of Program Operation (t WHWH1 ) Write Program Verify(2) Data = C0H; Stops Program Operations(3) Stand-by t WHGL Read Read Byte to Verify Programming Standby Wait for V PP Ramp to V PPH (1) Standby Compare Data Output to Data Expected Standby Wait for V PP Ramp to VPPL (1) Write Read Data = 00H, Resets the Register for Read Operations Y N Y Y N 0245_04 NOTES: 1. See DC Characteristics for the value of VPPH and VPPL. 2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command. 3. Refer of Principles of Operation. 4. Caution: The algorithm must be followed to ensure proper and reliable operation of the device. Figure 4. 28F020 Quick-Pulse Programming Algorithm |
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