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70353C 데이터시트(PDF) 45 Page - Microchip Technology

부품명 70353C
상세설명  Section 21. Enhanced Controller Area Network
PDF  76 Pages
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제조업체  MICROCHIP [Microchip Technology]
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70353C 데이터시트(HTML) 45 Page - Microchip Technology

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© 2008-2011 Microchip Technology Inc.
DS70353C-page 21-45
Section 21. Enhanced Controller Area Network (ECAN™)
21
21.7.1.2 ACCEPTANCE FILTER MASKS
As shown in Figure 21-11 and Figure 21-12, an acceptance filter mask determines which bits in
the incoming message identifiers are examined with the acceptance filters.
The acceptance filters optionally select one of the Acceptance filter masks using the Mask
Source Select (FnMSK<1:0>) mask select bits in the CiFMSKSEL1 and CiFMSKSEL2 registers:
• CiFMSKSEL1: ECAN Filter 7-0 Mask Selection Register
• CiFMSKSEL2: ECAN Filter 15-8 Mask Selection Register
The selection values for the FnMSK<1:0> bit are:
• 11 = Reserved
• 10 = Select acceptance filter mask 2
• 01 = Select acceptance filter mask 1
• 00 = Select acceptance filter mask 0
Table 21-1 is a truth table that indicates how each bit in the identifier is compared to the masks
and filters to determine if the message should be accepted or rejected. The mask bit essentially
determines which bits to apply the filter to. If any mask bit is set to ‘0’, that bit is automatically
accepted, regardless of the filter bit.
21.7.1.3 MESSAGE TYPE SELECTION
The Extended Identifier Enable bit (EXIDE) in the ECAN Acceptance Filter n Standard
Identifier register (CiRXFnSID<3>) enables reception of either SID or EID messages. The
Identifier Receive Mode bit (MIDE) in the ECAN Acceptance Filter Mask n SID register
(CiRXMnSID<3>) enables the EXIDE bit. If the MIDE bit is set, only the type of message selected
by the EXIDE bit is accepted. If the MIDE bit is clear, the EXIDE bit is ignored and all messages
that match the filter are accepted.
Table 21-2:
Message Type Selections
21.7.1.4 ACCEPTANCE FILTER CONFIGURATION
A sample code used to configure the acceptance filter 0 to receive the SID messages using the
acceptance filter mask register to mask SID<2:0> bits is shown in Example 21-4.
Table 21-1:
Acceptance Filter/Mask Truth Table
Mask (SIDn/EIDn)
Filter (SIDn/EIDn)
Message (SIDn/EIDn)
Accept or Reject bit n
0x
x
Accept
10
0
Accept
10
1
Reject
11
0
Reject
11
1
Accept
EXIDE
MIDE
Selection
0
1
Acceptance filter to check for SID
1
1
Acceptance filter to check for EID
x
0
Acceptance filter to check for SID/EID



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