AN4092 datasheet(13/38 Pages) STMICROELECTRONICS

13 / 38 page

AN4092

Power Management Controller (PMC)

Doc ID 023080 Rev 2

13/38

Use preferably a small plane to distribute VDD with a low parasitic inductance to each pin.

Using of multi-layer printed circuit board (PCB) with a separate layer dedicated to the

ground and another one to the voltages supply is also advised. If the small plane approach

is not possible, try to keep short and wide the traces between the ballast transistor and the

micro and the layout compact to reduce the parasitic.

Figure 5.

VDD distribution using a small plane example

Possibly, the ground plane should be adjacent to the VDD island, with a thin dielectric. This

build a good quality HF capacitor. Moat at least 1 to 3 mm between the different power

planes, never overlap them. Use multiple vias to connect to inner layers. This reduce the

inductance, being the vias parasitic inductance in parallel.

Decoupling capacitors are placed as close as possible to the VDD/VSS pair:

●

connected to both VDD and VSS pins (closest pins);

●

connected to each VDD/VSS pair.

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