UPD17708 datasheet(256/356 Pages) NEC

256 / 356 page

256

µPD17704, 17705, 17707, 17708, 17709

17.2 Input Selection Block and Programmable Divider

17.2.1 Configuration and function of input selection block and programmable divider

Figure 17-2 shows the configuration of the input selection block and programmable divider.

The input selection block selects an input pin and division mode of the PLL frequency synthesizer.

The VCOH or VCOL pin can be selected as the input pin.

The voltage on the selected pin is at the intermediate level (approx. 1/2 VDD). The pin not selected is internally

pulled down.

Because these pins are connected to an internal AC amplifier, cut the DC component of the input signal by

connecting a capacitor in series to the pin.

Direct division mode and pulse swallow mode can be selected as division modes.

The programmable divider divides the frequency of the input signal according to the value set to the swallow counter

and programmable counter.

The pin and division mode to be used are selected by the PLL mode selection register.

Figure 17-3 shows the configuration of the PLL mode selection register.

The value of the programmable divider is set by using the PLL data register via data buffer.

Figure 17-2. Configuration of Input Selection Block and Programmable Divider

Note

PLLSCNF flag

PLLMD1 flag

PLLMD0 flag

VCOH

VCOL

PLL disable signal

2-modulus prescaler

1/32, 1/33

Programmable counter

12 bits

-DET

Swallow counter

5 bits

DBF

PLL data register

12 bits

4 bits

Note

UPD17708 데이터시트(PDF) 256 Page - NEC