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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD17708 데이터시트(PDF) 89 Page - NEC |
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UPD17708 데이터시트(HTML) 89 Page - NEC |
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89 / 356 page  89 µPD17704, 17705, 17707, 17708, 17709 Table 9-1. Relationships between Peripheral Hardware and Data Buffer (2/2) At Reset Clock Function Power-ON WDT&SP CE Stop reset reset reset 00 0Note 0Note Sets compare voltage VADCREF of A/D converter Undefined Undefined Undefined Undefined Sets serial-out data and reads serial-in data FF FF Retained FF Sets modulo register value of timer 0 00 Retained 0 Reads count value of timer 0 counter FF FF Retained FF Sets modulo register value of timer 1 00 Retained 0 Reads count value of timer 1 counter FF FF Retained FF Sets modulo register value of timer 2 00 Retained 0 Reads count value of timer 2 counter 000 Retained Transfers data with address register Undefined Undefined Retained Retained Saves data of data buffer Undefined Undefined Retained Retained Sets division value (N value) of PLL 0000 Reads count value of frequency counter 1FF 1FF Retained 1FF Sets duty of output signal of D/A converter Sets duty of output signal of D/A converter (multiplexed with modulo register of timer 3) Sets modulo register value of timer 3 Note Value in hardare mode. “Retained” in software mode. |
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