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UPD17708 데이터시트(PDF) 270 Page - NEC

부품명 UPD17708
상세설명  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
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UPD17708 데이터시트(HTML) 270 Page - NEC

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µPD17704, 17705, 17707, 17708, 17709
17.6.3 Pulse swallow mode (VHF)
(1) Selecting division mode
Select the pulse swallow mode by using the PLL mode selection register.
(2) Pins used
The VCOH pin is enabled to operate when the pulse swallow mode is selected.
(3) Selecting reference frequency fr
Select the reference frequency by using the PLL reference frequency selection register.
(4) Calculation of division value N
Calculate N as follows:
N =
fVCOH
fr
fVCOH : Input frequency of VCOH pin
fr
: Reference frequency
(5) Example of setting PLL data
How to set data to receive broadcasting in the following FM band is described below.
Reception frequency
: 98.15 MHz (FM band)
Reference frequency
: 50 kHz
Intermediate frequency : +10.7 MHz
Division value N is calculated as follows:
N =
fVCOH
=
98.15 + 10.7
= 2177 (decimal)
fr
0.050
= 0881H (hexadecimal)
Set data to the PLL data register, PLL mode selection register, and PLL reference frequency selection register
as follows:
Caution The division value N is 17 bits long when the pulse swallow mode is selected, and the least
significant bit of the swallow counter is the bit 3 of the PLL mode selection register (PLLSCNF).
To set “0881H” as the division value N, the value to be actually set to the PLL data register
is “0440H”.
PLL data register (PLLR)
0
0
0
0
0
1
0
0 0
0
0
0
0
1
0
0
PLL mode
selection
register
PLL reference
frequency
selection register
Note
1
0
1
0
50 kHz
VHF
1
8
8
0
0
1
1
1
Note
PLLSCNF flag



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