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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD17708 데이터시트(PDF) 211 Page - NEC |
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UPD17708 데이터시트(HTML) 211 Page - NEC |
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211 / 356 page  211 µPD17704, 17705, 17707, 17708, 17709 15.5 Clock Generation Block The clock generation block outputs a basic clock to set the duty factor of each output signal. Two output frequencies, 1.125 MHz and 112.5 kHz, can be selected. 15.6 D/A Converter Output Wave (1) shows the relationship between the duty factor and output wave. (2) shows the output wave of each pin. Each output pin has a phase different from the others. (1) Duty and output wave (a) With 8-bit counter and 4.4 kHz selected (b) With 8-bit counter and 440 Hz selected 222 ns x = 0 x = 1 x = 2 x = 255 667 ns 888 ns 888 ns 227.56 s µ 2.22 s x = 0 x = 1 x = 2 x = 255 6.67 s 8.88 s 8.88 s 2.2756 ms µ µµ µ |
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