AN4149 datasheet(28/43 Pages) STMICROELECTRONICS

28 / 43 page

L4984D biasing circuitry

AN4149

28/43

DocID023523 Rev 2

In this way a change of the line voltage will cause an inversely proportional change of the

half sine amplitude at the output of the multiplier (if the line voltage doubles, the amplitude of

the multiplier output will be halved and vice versa) so that the current reference is adapted

to the new operating conditions with (ideally) no need for invoking the slow dynamics of the

error amplifier. Additionally, the loop gain will be constant throughout the input voltage

range, which improves significantly dynamic behavior at low line and simplifies loop design.

Actually, with other PFC embedding the voltage feed-forward, deriving a voltage

proportional to the RMS line voltage implies a form of integration, which has its own time

constant. If it is too small, the voltage generated will be affected by a considerable amount

of ripple at twice the mains frequency that will cause distortion of the current reference

(resulting in high THD and poor PF). If it is too large, there will be a considerable delay in

setting the right amount of feed-forward, resulting in excessive overshoot and undershoot of

the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-

off was required.

The L4984D implements an innovative voltage feed-forward which, with a technique that

makes use of just two external parts, overcomes this time constant trade-off issue

whichever voltage change occurs on the mains, both surges and drops. A capacitor CFF and

a resistor RFF, both connected from the pin VFF (pin #5) to ground, complete an internal

peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave

applied on pin MULT (pin #3). In this case following values have been selected:

Equation 80

In this way, in case of sudden line voltage rise, CFF will be rapidly charged through the low

impedance of the internal diode. In case of line voltage drop, an internal "mains drop"

detector enables a low impedance switch which suddenly discharges CFF avoiding a long

settling time before reaching the new voltage level. Consequently, an acceptably low

steady-state ripple and low current distortion can be achieved without any considerable

undershoot or overshoot on the preregulator's output like in systems with no feed-forward

compensation. This pin is internally connected to a comparator in order to provide the

brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (does not

latched) the L4984D and brings its consumption to a considerably lower level. The L4984D

restarts as the voltage at the pin rises above 0.88 V. These data have to be considered

during the MULT divider selection, setting the minimum operating voltage.

Please find here following the procedure to set properly the operating point of the multiplier

and the divider resistor values. Supposing a 60 uA (IMULT) current flowing into the multiplier

divider, the lower resistor value can be calculated:

Equation 81

A commercial value of 51 k

Ω for the lower resistor is selected. The upper resistor value can

now be calculated:

Equation 82

= M

MULT

multL

max

⋅

−

⋅

−

multL

multH

944

AN4149 데이터시트(PDF) 28 Page - STMicroelectronics

AN4149 데이터시트(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

데이터시트 다운로드

링크 URL