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UPD61P24CS 데이터시트(PDF) 10 Page - NEC |
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UPD61P24CS 데이터시트(HTML) 10 Page - NEC |
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10 / 36 page ![]() µPD61P24 10 11.3 KI Pin (P12) This is the 4-bit pin for key input. All of these pins are pulled down to the VSS level by PLA data. Figure 11-2. KI Pin Organization KI3 KI2 KI1 KI0 P2 11.4 KI Pull-Down Resistor Configuration V DD V SS N-ch V SS Pin Input signal PLA KI pull-down resistor switch Pull-down resistor P-ch When the pull-down resistor switch is turned on (set 1) by PLA data, pull-down resistor R is turned on. |
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