AN2555 - Application note

New features

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XCLKOUTDIV (E902h)

XBUS

Reset Value: --00h

2.3.1

Hardware impact

None.

2.3.2

Software impact

None if only CLOCKOUT is needed.

When the CLKOUT function is enabled by setting the CLKEN bit of the SYSCON register, by default the

CPU clock is output on P3.15. To have access to the XCLKOUTDIV register, and thus program the clock

pre-scaling factor, the XMISCEN bit of the XPERCON register and the XPEN bit of the SYSCON register

must be set.

2.4

Additional port input control: XPICON register

The possibility to select between TTL and CMOS-like input thresholds has been extended to the Ports 0,

1 and 5.

XREG

Reset Value: --00h

2.4.1

Hardware impacts

None.

2.4.2

Software impacts

None.

15

14

13

12

11

10

987

65432

10

--

-----

-

DIV

RW

Bit

Function

DIV

15

14

13

12

11

10

9

8

7

6

54

3210

-

----

----

-

P5HIN P5LIN P1HIN P1LIN P0HIN P0LIN

RW

RW

RW

RW

RW

RW

Bit

Function

Reset Value

PxLIN

Port x Lower Byte Input Level Selection

0:

Pins Px.7..0 switch on standard TTL input levels

1:

Pins Px.7..0 switch on CMOS input levels

0

PxHIN

Port x Higher Byte Input Level Selection

0:

Pins Px.15..8 switch on standard TTL input levels

1:

Pins Px.15..8 switch on CMOS input levels

0