AN2555 - Application note

Modified registers

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3

Modified registers

3.1

XPERCON register

In the ST10F276Z5, new bits have been added with regards to the additional XPeripherals.

The XPERCON register allows the XBUS peripherals to be separately selected and made visible to the

user by means of the corresponding bits. If not selected (not activated with a bit of XPERCON) before

the XPEN bit in SYSCON is set, the corresponding address space, port pins and interrupts are not

occupied by the peripheral, and thus this peripheral is not visible and not available.

SFR

Reset Value: --05h

SFR

Reset Value: -005h

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

---

--

--

--

--

RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN

RW

RW

RW

RW

RW

15

14

13

12

11

10

98

7654321

0

-

----

XMIS

CEN

XI2C

EN

XSSC

EN

XASC

EN

XPW

MEN

XFLA

SHEN

RTCE

N

XRA

M2EN

XRA

M1EN

CAN2

EN

CAN1

EN

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Bit

number

Bit name

Function

0

CAN1EN

CAN1 Enable Bit

’0’: Accesses to the CAN1 and its functions are disabled (P4.5 and P4.6 pins

can be used as general purpose IOs)

’1’: The CAN1 is enabled and can be accessed.

1

CAN2EN

CAN2 Enable Bit

’0’: Accesses to the CAN2 and its functions are disabled (P4.4 and P4.7 pins

can be used as general purpose IOs)

’1’: The CAN2 is enabled and can be accessed.

2

XRAM1EN

XRAM1 Enable Bit

’0’: Accesses to the XRAM1 block are disabled, external access performed.

’1’: The on-chip XRAM1 is enabled and can be accessed.

3

XRAM2EN

XRAM2 Enable Bit

’0’: Accesses to the XRAM2 block are disabled, external access performed.

’1’: The on-chip XRAM2 is enabled and can be accessed.

4RTCEN

RTC Enable Bit

‘0’: Accesses to the Real Time Clock are disabled, external access

performed.

‘1’: The on-chip Real Time Clock is enabled and can be accessed.

5

XFLASHEN

XFLASH Enable Bit

‘0’: Accesses to the on-chip XFLASH are disabled, external access

performed.

‘1’: The on-chip XFLASH is enabled and can be accessed.