AN2633 datasheet(17/48 Pages) STMICROELECTRONICS

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AN2633

Power supply and clocks

17/48

As a result the time required to enter Sleep mode depends both on the oscillator clock, on

the CPUCLK clock and on the slowest clock set for the peripherals coming out of the Clock

Control Unit according to the following equation:

SLEEP = 17 * (tOSC) + 14 * (tSLOWEST_PERIPH_CLK)+ 6 * (tCPUCLK)

Workarounds:

Take account of the maximum time required to enter Sleep mode (Tsleep) in your specific

application.

Caution:

During this t

SLEEP time any wake-up input is ignored. In addition, if a Wake-up or interrupt

event occurs immediately after setting the power management register and before the mode

becomes internally effective, it could freeze the device.

Table 2.

CCU output clocks that determines the entry time (tSLEEP)

CCU_OUT

Description

Control register

BRCLK

Baud Rate Clock to the UART

SCU_CLKCNTR

TIMO1CLK

Timer 0-1 clock

SCU_CLKCNTR

TIM23CLK

Timer 2-3 clock

SCU_CLKCNTR

EMICLK

EMI clock

SCU_CLKCNTR

FMICLK

FMI clock

SCU_CLKCNTR

WDG

Watchdog clock

WDG_CR (EE)

HCLK

AHB clock

SCU_CLKCNTR

PCLK

APB clock

SCU_CLKCNTR

CPUCLK

ARM core clock

SCU_CLKCNTR

USBCLK

USB Clock

SCU_CLKCNTR

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