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AN2674 데이터시트(PDF) 17 Page - STMicroelectronics

부품명 AN2674
상세설명  PCB layout guidelines for SPEAr3xx
PDF  22 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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AN2674
Using an external clock
Doc ID 14204 Rev 2
17/22
5
Using an external clock
Using an external clock source to drive SPEAr3xx is accomplished by using a compatible
clock generator that meets the necessary jitter and waveform specifications, and configuring
the internal clock for an external source.
The external clock signal is applied to oscillator MCLK_XI pin. This is a digital signal with a
nominal voltage swing between 0 V and 2.5 V. If a clock source with a different voltage swing
is used, then a voltage translator must be used. A 3.3 V signal should not be applied to the
MCLK_XI pin.
5.0.1
External clock signal requirements
The clock signal specifications are listed in the table below.
5.0.2
Voltage translation of external clock
If the external clock's output has a signal swing of other than 2.5 V, then some form of level
translation must be used on the signal before it is applied to MCLK_XI. An IC level translator
can be used, or a resistor voltage divider network can be used if the source has a 3.3 V
swing. The level translator must provide a stable, monotonic, and clean waveform to the
clock input.
The resistor network must account for several conflicting requirements. First, the correct
resistor ration must be used to provide the correct levels, and second, because the
connection between the clock source and SPEAr3xx is a trace on a PCB, which is a
transmission line and therefore exhibits transmission line behavior, the resistor values used
in the divider must adequately control reflections. The goal is to provide a clean waveform at
MCLK_XI with minimal overshoot or ringing. Figure 7 depicts the general network
configuration.
Table 5.
External clock signal requirements for oscillator MCLK_XI input
Symbol
Description
Min
Typ
Max
Units
VDD_OSC
Oscillator power supply voltage
2.5
V
VIH
High input voltage (1)
1.
Because the MCLK_IN is the input to the oscillator gain stage, VIL and VIH levels and rise/fall time are more
restricted than digital inputs.
VDD_OSC - 0.2
V
VIL
Low input voltage (1)
0.2
V
tRISE
Rise time of clock input signal
3
10
ns
tFALL
Fall time of clock input signal
3
10
ns
fCLK
Frequency of external source
30.000
MHz



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