AN3114 datasheet(22/43 Pages) STMICROELECTRONICS

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Integrated LCD controller

AN3114

22/43

Doc ID 16829 Rev 3

Figure 12.

Resistive network (internal booster)

●

In case of 1/2 bias, one voltage level (1/2 VLCD) is generated and node b voltage is 1/2

VLCD.

●

In case of 1/3 bias, two intermediate voltage levels (1/3 VLCD, 2/3 VLCD) are generated:

–

node a is 1/3 VLCD

–

node b is 2/3 VLCD

●

In case of 1/4 bias (medium+ and high density STM8L152xx and STM8L162xx devices

only), three intermediate voltage levels (1/4 VLCD, 1/2 VLCD and 3/4 VLCD) are generated:

–

node a is 1/4 VLCD

–

node b is 1/2 VLCD

–

node c is 3/4 VLCD.

3.2

Optimizing power consumption

When the LCD controller operates in run mode, decreasing the power consumption results

in a lower contrast. As a consequence, the contrast adjustment methods described in

Section 3.1.3 can also be used to adjust the power consumption.

When the internal booster is used, the power consumption can be reduced by minimizing

the period of time during which the RL divider is enabled (drive time). However, the drive

time to achieve a satisfactory contrast may be longer with a high internal resistance.

However, the STM8AL3Lxx, STM8L152xx, and STM8L162xx microcontrollers allow the

LCD controller to operate in all low power modes except for Halt mode.

VLC D

VSS

bias 1/3

node b

bias 1/2 or bias 1/4

bias 1/3

bias 1/4

STATIC

MS19205V1

node a

node c

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