AN3270

AES hardware accelerator operation modes

Doc ID 17919 Rev 2

5/23

Figure 3.

AES algorithm in encryption mode

1.

The AES peripheral clock must be enabled to allow write access to the AES registers.

2.

Mode configuration must be done before enabling the AES.

3.

If required, the Computation Complete interrupt can be enabled using the Computation Complete Interrupt

Enable (CCIE) bit.

4.

The AES hardware accelerator requires the 16 bytes of data (128 bits) to be written/read from MSB (16th

data byte) to LSB (1st data byte) that is why the Counter is initialized to 0.

Enable AES clock

(1)

Configure AES peripheral:

Select encryption mode

(2)

Enable computation complete

interrupt

(3)

Enable AES to start processing

Counter = 0

Write encryption key EK[counter]

in DINR register

Write plain text PT[counter]

in DINR register

Counter = 16?

(4)

Is computation complete?

Counter++

Counter = 16?

(4)

End

Counter = 0

Read cypher text CT[counter]

from DOUTR register

Input phase

Computation phase

Output phase

Counter++

MS19717V1