RM0319 datasheet(74/368 Pages) STMICROELECTRONICS

74 / 368 page

Multiport DDR controller (MPMC)

RM0319

74/368

Doc ID 022640 Rev 3

Priority relaxing

With reference to Table 25, it is evident that ports at lower priority levels will not win

arbitration in weighted round-robin arbitration unless there are no higher priority requests.

This could mean that, in a situation where high priority requests are being received

continuously, lower priority requests could be locked out indefinitely. To avoid this scenario

and control the arbitration latency for lower-priority ports, it is possible to disable priority

groups temporarily. This is known as priority relaxing, and it is a time-controlled function.

Each higher priority group will be temporarily disabled when the pre-set counter value for the

lower priority group has been reached and a request is waiting. The ahbX_priority_relax

parameters set the counter value for port X at which the priority relax condition will be

triggered.

The timing counters inside each port are controlled by the

weighted_round_robin_latency_control parameter. When the latency control bit is set to

1'b1, the timing counters are free-running. Any timing counter may hit its

ahbX_priority_relax value at any point. Whenever this happens, higher-priority groups are

disabled to allow a waiting request for this port to be processed. This brings a random

latency for each port, but the maximum latency is fixed at the ahbX_priority_relax value.

If the current port does not have any commands waiting when the timing counter hits the

relax value, the counter will be reset and the arbiter will works normally.

When the weighted_round_robin_latency_control parameter is cleared to 1'b0, the timing

counters only count while that port has a waiting request that is not being processed. In this

case, when the port's ahbX_priority_relax parameter value is reached, all priority groups at

priority levels higher than the waiting request are disabled. This port's command is granted

arbitration and is moved through to the core. Since the priority relax parameters and

counters are associated with individual ports, it is possible that multiple priority relax

counters could reach their specified value simultaneously. In this case, the lower priority

Table 25.

System E operation

Cycle

Port Requesting

Arbitration

Winner

Next Counter

Next Scan Order

P0 P1 P2 P3 P4 P5

Priority 0: P0-P1-P2-P3

Priority 1: P4-P5

0P0-P1-P2-P3-P4-P5

P0-P1-P2-P3-P4-P5

0P0-P1-P3-P2-P4-P5

P0-P1-P3-P2-P4-P5

0P0-P1-P3-P2-P4-P5

P0-P1-P3-P2-P4-P5

0P0-P1-P3-P2-P4-P5

0P0-P1-P3-P2-P5-P4

1P0-P1-P3-P2-P5-P4

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