RM0319 datasheet(27/368 Pages) STMICROELECTRONICS

27 / 368 page

RM0319

ARM926EJ-S

Doc ID 022640 Rev 3

27/368

3.3

Functional description

Figure 2.

ARM926EJ-S block diagram

Note:

The co-processor interface and the TCM interface are not used.

3.3.1

Memory management unit (MMU)

A single set of two-level page tables stored in main memory is used to control the address

translation, permission checks, and memory region attributes for both data and instruction

accesses.

The memory management unit uses a single unified translation look aside buffer (TLB) to

cache the information held in the page tables. To support both sections and pages, there are

two levels of address translation, and the MMU puts the translated physical addresses into

the MMU TLB.

The MMU TLB consists of two parts:

●

The main TLB, which is a two-way, set-associative cache for page table information. It

has 32 entries per way for a total of 64 entries.

●

The lockdown TLB, which is an eight-entry fully-associative cache that contains locked

TLB entries. Locking TLB entries can ensure that a memory access to a given region

never incurs the penalty of a page table walk.

DRDATA

IRDATA

ETM

interface

RDATA

Coprocessor

interface

WDATA

INSTR

ARM9EJ-S

FCSETLB

MMU

ICACHE

IEXT

DCACHE

Cache

TAGRAM

Write back

Write buffer

DEXT

Write buffer

External Coprocessor

Interface

CPUINSTR

CPUOUT CPUIN

TCM

interface

Bus

Interface

unit

DROUTE

IROUTE

DRWDATA

Data

AHB

Interface

Intruction

AHB

Interface

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