RM0319 datasheet(26/368 Pages) STMICROELECTRONICS

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ARM926EJ-S

RM0319

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Doc ID 022640 Rev 3

ARM926EJ-S

This chapter focuses on ARM926EJ-S functionality and operation.

For technical details about the programmable registers related to the ARM926EJ-S, refer to

the system configuration registers (MISC) in the following companion document:

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RM0321: SPEAr320S address map and registers

3.1

Overview

The ARM926EJ-S is a powerful processor, targeted for multitasking applications. Belonging

to the ARM9 general purpose family of microprocessors, its main outstanding feature is the

memory management unit, which provides virtual memory features, making it also

compliant with advanced operating systems, like Linux.

The ARM926EJ-S supports the 32-bit ARM and the 16-bit Thumb instruction sets, enabling

the user to trade off between high performance and high code density. It includes features

for efficient execution of byte code Java mode. Additionally, it has the ARM debug

architecture and includes logic to assist in software debug.

3.2

Main features

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Max CPU frequency 333 MHz (downward scalable)

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MMU

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16 Kbyte of instruction cache + 16 Kbyte of data cache

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AMBA bus interface

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JTAG and ETM9 (embedded Trace macro-cell) for debug, Medium+ version

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