RM0319 datasheet(144/368 Pages) STMICROELECTRONICS

144 / 368 page

Fast Ethernet port (MII0)

RM0319

144/368

Doc ID 022640 Rev 3

12.3.6

Power management module (PMT)

This section describes the power management (PMT) mechanism as supported by the

MAC. PMT supports the reception of network (remote) wake-up frames and Magic Packet

frames. PMT does not perform the clock gate function, but generates interrupts for wake-up

frames and Magic Packets received by the MAC. The PMT block sits on the receiver path of

the MAC and is enabled with remote wake-up frame enable and Magic Packet enable.

These enables are in the PMT Control and Status Register (Register11, MAC) and are

programmed by the Application.

12.3.7

DMA descriptors

The DMA Controller operates two descriptor lists, one for transmission and one for

reception. The base address of each list is written into DMA Register3 (Receive Descriptor

List Address) and Register4 (Transmit Descriptor List Address), respectively.

Each descriptor list (both for transmission and for reception) consists of a set of descriptor,

and each descriptor is provided with the following fields:

●

The status of the received/transmitted frames together with descriptor ownership

information

●

A set of control bits

●

The byte-count of the two pointed data buffers

●

The address pointers of the two data buffers

Depending on the contents of the 2nd data buffer of the last descriptor in the list, two

different lists can result (as depicted in Figure 45.)

●

A ring structure: the list is implicitly forward linked, each descriptor points to two data

buffers, and the last descriptor points back to the first entry of the list;

●

A chain structure: the list is explicitly forward linked by using the 2nd address pointer

of each descriptor to point the next descriptor in the list.

RM0319 데이터시트(PDF) 144 Page - STMicroelectronics