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RM0319 데이터시트(PDF) 153 Page - STMicroelectronics

부품명 RM0319
상세설명  SPEAr320S architecture and functionality
PDF  368 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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RM0319 데이터시트(HTML) 153 Page - STMicroelectronics

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RM0319
Fast Ethernet port (MII0)
Doc ID 022640 Rev 3
153/368
The signal pmt_intr_o reflects the combination of the value PMT_INTR in the MAC interrupt
status register (Interrupt Status Register (Register14, MAC), bit 3) and the value
PMT_INTR_MASK in the MAC interrupt mask register (Interrupt Mask Register (Register
15,MAC), bit 3).
Interrupts can be generated from the MAC Core as a result of various events in the optional
modules in it (for example MMC and PMT modules). These interrupt events are combined
with events in the DMA on the sbd_intr_o signal. Infact the signal pmt_intr_o is also used to
drive the signal sbd_intr_o (GPI in the figure above).
In the same way the MMC block through MMC_INTR (controlled by Interrupt Status Register
(Register14, MAC), bit 4) drives the sbd_intr_o signal (GMI in the figure above).
The other events in the DMA that drive the sbd_intr_o signal are produced by the
combinations of status register bits and interrupt mask bits (listed correspondingly in the
Status Register (Register5, DMA) and Interrupt Enable Register (Register7, DMA)).
12.6
Programming examples
How to initialize DMA
1.
Write to DMA register0 (Bus Mode) to set the host bus access parameters.
2.
Write to DMA register7 (Interrupt Enable) to mask needless interrupt causes.
3.
Create the Transmit And Receive descriptor lists into the host physical memory space.
4.
Write to both DMA register3 (Receive Descriptor List Address) and register4 (Transmit
Descriptor List Address) providing the DMA with the starting address of each descriptor
list.
5.
Write to MAC register1 (MAC Frame Filter), register2 (Hash Table High) and register3
(Hash Table Low) for described filtering options.
6.
Write to MAC register0 (MAC configuration) to configure and enable the Transmit And
Receive operating modes. The PS and DM bits are set based on the auto-negotiation
result (read from the PHY).
7.
Write to DMA register6 () setting bits [1] SR and [13] ST to start reception and
transmission, respectively.



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