RM0319 datasheet(173/368 Pages) STMICROELECTRONICS

173 / 368 page

RM0319

Fast Ethernet ports (RMII0/RMII1/MII1)

Doc ID 022640 Rev 3

173/368

13.5

Interrupts

There are 14 interrupt conditions that are detected within the MACB. The common interrupt

(which is an ORed version of the 14 interrupts) and the Wake-Up on LAN (won) interrupt

from the two MACBs are all ORed and connected to line 1 of the Vectored Interrupt

Controller (VIC). For the source of interrupt on line 1 of the VIC, you can refer to the Interrupt

status register (0xB300_0004) description which is external to the MACB blocks. This a

read-only register and as soon as the interrupt is cleared at its source, the status is updated

in this register.

This single interrupt is passed through a further level of interrupt collection (Common

Interrupt Status Register). On receipt of the interrupt signal, the CPU enters the interrupt

handler. To ascertain which interrupt has been generated, read the external Common

Interrupt Status Register and then the internal Interrupt Status Register.

Note:

The Interrupt Status Register internal to the MAC will clear itself when read.

At reset all interrupts are disabled. To enable an interrupt, write to interrupt enable register

with the pertinent interrupt bit set to 1. To disable an interrupt, write to interrupt disable

disabled, read interrupt mask Register: if the bit is set to 1, the interrupt is disabled.

13.6

Programming examples

Prior to configuring and initializing the MACB, the interface signals must be enabled on the

external pins. The procedure for enabling the interface depends on the configuration mode

of the shared PL_GPIO pins.

Refer to the datasheet for a description of the related configuration modes (Automation

Networking mode, Automation expansion mode, Extended mode and Small Printer mode).

13.6.1

Enabling the MII interface

To enable MII:

In “Mode 2 MII Automation Networking" mode:

Check bit [0] in the RASCFG Extended Control Register (0xB3000018) is set to '0'

Write 0x1 to bits [2:0] in the RASCFG Control Register (0xB3000010)

In “Extended" mode”

Write 0x1 to bit [0] in the RASCFG Extended Control Register (0xB3000018)

Check bit [19:18] is set to '00' in RASCFG Extended Control Register

(0xB3000018)

Configure "IP Port select for GPIO_x to GPIO_y in the RASCFG Extended Mode

2. Go to Initializing and configuring MACB on page 174

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