RM0319 datasheet(335/368 Pages) STMICROELECTRONICS

335 / 368 page

RM0319

Power, reset and clock control

Doc ID 022640 Rev 3

335/368

Refer to the description of the AMEM_CFG_CTRL register and the ahbX_fifo_type_reg

parameter in the MPMC chapter for configuration details.

30.5.5

Bus clocks

Through the miscellaneous CORE_CLK_CFG and PRPH_CLK_CFG registers, you can

define:

●

the ratio between the CPU clock and its HCLK

●

the ratio between the AHB and the APB clock

●

the source for the peripheral clock

By default, this is derived from the fixed frequency of 48 MHz avoiding problems in case that

the bus clock changes value because of different system states or because of different PLL

settings.

Peripheral clock gating

The miscellaneous PERIP1_CLK_ENB register provides control bits allowing the software

to enable or disable the clock for each peripheral for sophisticated power management.

30.5.6

Watchdog module clock enable generation

Enable signals are generated by the system controller to allow the watchdog module to be

clocked at a rate that is independent of the system clock SYS_CLK. In particular, the enable

signals are generated by sampling a free-running, constant frequency input clock and

generating an active high pulse for a single SYS_CLK clock cycle on each rising edge of the

input clock.

The supported module enable signals are:

●

WDCLKEN for the watchdog module clock enable.

The enable signal for the watchdog module is generated from the REFCLK input, as defined

by the WDogEnOv bit in the system control register (SCCTRL).

30.5.7

RAS clock

The CLCD, SDIO and FSMC IPs, present in the RAS subsystem, operate at HCLK clock

frequency. While SPP, SSP, CAN, PWM and UART operate at PCLK clock frequency. Other

clock frequencies are shown in the diagram below.

Table 120.

DDR_CLK source selection

mctr_clk_sel bits

System clock source

(output of M4 multiplexer (see Figure 111

)

000

HCLK

001

2x HCLK

010

Reserved

011

PLL2

1xx

Reserved

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