SW methods

AN4655

12/21

DocID027483 Rev 1

2.4.2

UART

SW emulation of UART channel requires proper timing control as the data flow is

asynchronous. Data transmission and reception are two quite independent and

unsynchronized processes provided on two separated unidirectional data lines (Tx and Rx)

driven exclusively by the transmitter.

Usually, any synchronization or timing issue should prevent timing errors larger than 30%

within every transacted bit rate interval. When 10 bits are transacted within a character

frame, the internal clock difference ratio between transmitter and receiver should not exceed

3% to handle the last transacted bit correctly. The defined rate and bit protocol are

configurable.

Physical interface is mostly defined by additional communication standards like

RS232/422/485.

Modem operation capability can be supported by additional status signals like CTS/RTS. No

addressing or acknowledgment control is implemented.

Character framing is partially configurable, NRZ format is used. The frame is started by

single start bit followed by 5-9 data bits with optional parity bit included and closed by 1-2

stop bits. If data line is held at idle longer than a character time a break condition can be

detected. Bit sampling is usually provided in the middle of the bit interval and can include

few samples of the same bit. It can raise noise, frame (stop) or parity framing errors.

Receiver can face overrun error, too.

Optional API can integrate single data buffering or more complex FIFO structures for both

transmitter and receiver.

2.4.3

I2C

SW emulation of I2C channel is the most complex one as wide range of aspects has to be

considered.

A specific timing is required in dependency of selected mode, even if a synchronous

protocol is used. This applies especially for Standard mode (for which rates are slower, up to

100 kbit/s), where duration of low and high period of SCL clock signal and margin between

data SDA and clock SCL signals change during Start and Stop conditions have to be kept at

The output stages of the bidirectional SDA and SCL signals should have an open-drain or

open-collector to perform the wired-AND function. The standard allows to connect sources

with different supply levels.

The protocol includes 10-bits or 7-bits addressing read and write modes, bus arbitration

supporting multi master communication, data acknowledgment, clock stretching and clock

synchronization procedures. The emulation task can be dramatically simplified when the

application doesn’t need to support some of these requirements.

If API is applied, it is based mostly on more complex interface which collects all the

necessary information to handle the protocol, data transfer and raised events. Misplaced

start or stop condition (bus error), acknowledge failure and arbitration loss (at multi master

system) are the communication errors usually signaled by the API. A slave receiver can face

a data overrun when no clock stretching is applied, too.