SW methods

AN4655

14/21

DocID027483 Rev 1

receive frame. All even compare interrupts are discarded. After the stop bits of the frame are

sampled, the Rx pin is switched back to input capture mode and waits for the next frame

start condition. The detection of noise while the stop bits are being sampled should cause a

frame error. If a noise is detected during start bit, the receive process should be aborted and

the Rx pin switched back to input capture mode while waiting for the next falling edge

capture.

User can build an API interface upon this low level HW abstraction level. It can include the

UART channel initialization, enable and disable Rx and Tx channels, read and write the data

flow (e.g. control the data buffers) and check the transactions’ status. Size of data, parity

control number of stop bits or other control can be solved on pre-compilation level by

conditional compilation to speed up the code when these features are not used.

2.5.2

SPI bit-banging sequence

This is an example of procedure controlling SPI master full duplex 8 bits data frame

transaction (MSB first format). The procedure can be written based as a sequence of

applied macros to achieve a maximum speed, even if it doesn’t fully respect good common

software practice requiring structured code organization (e.g. collect repeated parts at loops

or subroutines).

/**

* @brief SPI master RW bit-bang

* @param unsigned char wb - data to transmit

* @retval unsigned char rb – data received

*/

unsigned char SPI_master_8_bit_data_RW (unsigned char wb)

{

unsigned char msk = 0x80;

unsigned char rb = 0;

do

{

#if CPHA=0

miso_control(rb);

mosi_control(wb);

setup_dly();

sck_odd_edge_control();

half_bit_dly();

sck_even_edge_control();

setup_dly();

#else /* CPHA=1 */

sck_odd_edge_control();

setup_dly();

miso_control(rb);

mosi_control(wb);

setup_dly();

sck_even_edge_control();

half_bit_dly();