22

LTC1418

Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using

the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)

two zeros. The MSB (D13) will be valid on the first rising

and the first falling edge of the SCLK. D12 will be valid on

the second rising and the second falling edge as will all

the remaining bits. The data may be captured on either

edge. The largest hold time margin is achieved if data is

captured on the rising edge of SCLK.

BUSY gives the end of conversion indication. When the

LTC1418 is configured as a master serial device, BUSY

can be used as a framing pulse and to three-state the

SCLK

1418 F21

LTC1418

BUSY (= RD)

CLKOUT ( = SCLK)

BUSY

CONVST

CONVST

RD

SCLK

CLKOUT

EXT/INT

26

24

23

17

18

20

25

19

CS

1418 F22a

µP OR DSP

(CONFIGURED

AS SLAVE)

OR

SHIFT

REGISTER

D12

D11

D11

D12

CAPTURE ON

RISING CLOCK

D13

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

FILL

ZEROS

D13

1

23456789

10

11

12

13

14

15

16

1

2

3

D13

D13

D12

D11

Hi-Z

Hi-Z

DATA N

DATA (N – 1)

(SAMPLE N)

(SAMPLE N + 1)

CS = EXT/INT = 0

CLKOUT (= SCLK)

CONVST

SAMPLE

HOLD

HOLD

1418 F22b

BUSY (= RD)

CLKOUT

(= SCLK)

CAPTURE ON

FALLING CLOCK