24

LTC1418

clock to EXTCLKIN. The same clock is also applied to SCLK

to provide a data shift clock. To maintain accuracy the

conversion clock frequency must be between 30kHz and

4.5MHz.

It is not recommended to clock data with an external clock

during a conversion that is running on an internal clock

because the asynchronous clocks may create noise.

Serial Data Output After a Conversion

Using Internal Conversion Clock and External Data Clock.

In this mode, data is output after the end of each conver-

sion but before the next conversion is started (Figure 24).

The internal clock is used as the conversion clock and an

external clock is used for the SCLK. This mode is useful in

applications where the processor acts as a master serial

device. This mode is SPI and MICROWIRE compatible. It

LTC1418

BUSY

CONVST

26

24

19

20

25

23

17

CONVST

RD

SCLK

EXT/INT

CS

1418 F24a

µP OR DSP

INT

C0

SCK

MISO

12 11 10 987654321

0

FILL

ZEROS

D13

123456789 10 11 12 13 14 15 16

Hi-Z

DATA N

Hi-Z

(SAMPLE N)

CS = EXT/INT = 0

CONVST

HOLD

SAMPLE

1418 F24b

BUSY

SCLK

RD

D11

D12

CAPTURE ON

RISING CLOCK

D13

SCLK

CAPTURE ON

FALLING CLOCK

Figure 24. Internal Conversion Clock Selected. Data Transferred After Conversion

Using an External SCLK. BUSY

↑ Indicates End of Conversion