25

LTC1418

also allows operation when the SCLK frequency is very low

(less than 30kHz). To select the internal conversion clock

tie EXT/INT low. The external SCLK is applied to SCLK. RD

can be used to gate the external SCLK, such that data will

data transfer. If more than 16 SCLKs are provided, more

zeros will be filled in after the data word indefinitely.

LTC1418

BUSY

CONVST

CONVST

RD

EXTCLKIN

SCLK

EXT/INT

CS

5V

25

16

24

23

17

26

19

20

1418 F25a

µP OR DSP

CLKOUT

INT

C0

SCK

MISO

123456789 10 11 12 13 14 15 16

CS = 0, EXT/INT = 5

CONVST

EXTCLKIN

HOLD

SAMPLE

BUSY

SCLK

RD

123456789 10 11 12 13 14 15 16

1

2

34

12 11 10 987654321

0

FILL

ZEROS

D13

Hi-Z

DATA N

Hi-Z

(SAMPLE N)

1418 F25b

D11

D12

CAPTURE ON

RISING CLOCK

D13

SCLK

CAPTURE ON

FALLING CLOCK

Figure 25. External Conversion Clock Selected. Data Transferred After Conversion

Using an External SCLK. BUSY

↑ Indicates End of Conversion

Using External Conversion Clock and External Data

Clock. In Figure 25, data is also output after each conver-

sion is completed and before the next conversion is

started. An external clock is used for the conversion clock

and either another or the same external clock is used for

the SCLK. This mode is identical to Figure 24 except that

an external clock is used for the conversion. This mode