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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD78P324LP 데이터시트(PDF) 45 Page - NEC |
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UPD78P324LP 데이터시트(HTML) 45 Page - NEC |
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45 / 80 page  µPD78P324, 78P324(A) 45 (3) µPD78P324(A1) Electrical Specifications (5/9) AC Characteristics (TA = –40 to +110 °C, VDD = +5 V ±10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter Symbol Condition MIN. MAX. Unit System clock cycle time tCYK 160 250 ns Address setup time (vs. ASTB ↓)tSAST 40 ns Address hold time (vs. ASTB ↓)tHSTA 50 ns Address → RD ↓ delay time tDAR 120 ns RD ↓ → address float time tFRA 10 ns Address → data input time tDAID 310 ns RD ↓ → data input time tDRID 165 ns ASTB ↓ → RD ↓ delay time tDSTR 60 ns Data hold time (vs. RD ↑)tHRID 0ns RD ↑ → address active time tDRA 68 ns RD low-level width tWRL 191 ns ASTB high-level width tWSTH 55 ns Address → WR ↓ delay time tDAW 120 ns ASTB ↓ → data output time tDSTOD 120 ns WR ↓ → data output time tDWOD 40 ns ASTB ↓ → WR ↓ delay time tDSTW 60 ns Data setup time (vs. WR ↑)tSODW 191 ns Data hold time (vs. WR ↑)tHWOD 50 ns WR ↑ → ASTB ↑ delay time tDWST 60 ns WR low-level width tWWL 195 ns |
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